1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device. In particular, the present invention relates to a manufacturing method of a semiconductor device having a self-aligned high-performance bipolar transistor and a dual gate high-performance CMOS transistor on the same substrate.
2. Description of Related Art
A conventional BiCMOS semiconductor device having a bipolar transistor and a CMOS transistor on the same substrate has an advantage that high operation speed and high load driving ability of the bipolar transistor and a high integration density and lower power consumption of the MOS transistors can be realized simultaneously. However, to form a high-performance bipolar transistor and high-performance MOS transistors on the same substrate, there are problems that the number of manufacturing steps and the number of masks increase.
FIGS. 15A-15D to FIGS. 18A-18C show a process of a conventional manufacturing method of a BiCMOS semiconductor device having a self-aligned high-performance bipolar transistor and a CMOS transistor on the same substrate.
As shown in FIG. 15A, field oxide films 101 are formed by a LOCOS method or the like on a semiconductor substrate 100 having buried layers and well layers 102a and 102b are formed. Then, as shown in FIG. 15B, an insulating film 153 to become gate oxide films of MOS transistors is formed. As shown in FIG. 15C, a doped polysilicon film 156 to become the gates of the MOS transistors is deposited on the insulating film 153 and an insulating film 157 of TEOS or the like is deposited on the doped polysilicon film 156. Then, the gates of the MOS transistors are formed by using a resist pattern 158. As shown in FIG. 15D, LDD layers 159 and 160 of the MOS transistors are formed. Then, frames 161 are formed on the side faces of the gates of the MOS transistors by depositing an insulating film of TEOS or the like and dry-etching it. Then, source/drain layers 162 and 163 of the MOS transistors are formed by injection.
As shown in FIG. 16A, the MOS transistor forming region is protected by depositing an insulating film 164 of TEOS or the like. As shown in FIG. 16B, a polysilicon film 165 is deposited and an impurity BF2 106 (170) is implanted into the polysilicon film 165 over its entire area. Subsequently, as shown in FIG. 16C, an insulating film 166 of TEOS or the like is deposited on the entire surface.
As shown in FIG. 17A, after performing photolithography, a base lead-out electrode is formed by etching the polysilicon film 165 and the insulating film 166. Then, after an oxide film 109 is formed by oxidation, an external base layer 110 is formed by diffusing the impurity in the polysilicon film 165 into the semiconductor film 100. As shown in FIG. 17B, an intrinsic base layer 110a is formed by implanting an impurity BF2. Then, a frame is formed on the side face of the base lead-out electrode by depositing an insulating film 167 of TEOS or the like and etching it as shown in FIG. 17C. As shown in FIG. 17D, a polysilicon film 169 to become an emitter lead-out electrode of an NPN transistor is deposited and an impurity 168 of As or the like is implanted over the entire area.
As shown in FIG. 18A, after a desired region is defined by photolithography, an emitter lead-out electrode 172 of the NPN transistor is formed by dry etching. As shown in FIG. 18B, an interlayer insulating film 171 such as a TEOS/BPSG/TEOS film is deposited and its surface is planarized by subjecting it to reflow. Further, an emitter layer 173 is formed by diffusing the impurity into the semiconductor substrate 100 from the emitter lead-out electrode 172. Finally, interconnections 174 etc. are formed as shown in FIG. 18C.
As described above, the MOS region is protected by depositing the insulating film 164, whereby damage that would otherwise occur in later forming the NPN transistor is prevented and thereby the characteristics of the MOS transistors are prevented from being deteriorated.
The above-described conventional BiCMOS semiconductor device having the bipolar transistor and the CMOS transistor on the same substrate has a problem that the measure to prevent deterioration in transistor characteristics makes the process complex and increases the number of manufacturing steps. To decrease the number of manufacturing steps even by a small number, the gate electrodes of both of the NMOS transistor and the PMOS transistor are given N-type conductivity and the PMOS transistor is made a buried channel type. This results in problems that the leak current of the PMOS transistor increases and the threshold voltage Vth is difficult to control.
The present invention has been made to solve the above problems in the art, and an object of the invention is therefore to provide a manufacturing method of a semiconductor device and which can form high-performance bipolar transistors and high-performance MOS transistors on the same substrate while minimizing increases in the number of manufacturing steps and the number of masks.
According to an aspect of the present invention, there is provided a manufacturing method of a semiconductor device which forms bipolar transistors and MOS transistors on the same semiconductor substrate, comprising the steps of a first insulating film forming of forming separated first insulating films on a major surface of the semiconductor substrate; a second insulating film forming of forming a second insulating film on the semiconductor substrate and the first insulating films; a second insulating film removing of removing a portion, on the semiconductor substrate, of the second insulating film in a region where to form a base of a first conductivity type bipolar transistor; forming a first polysilicon film on a second-insulating-film-removed portion of the semiconductor substrate and a remaining portion of the second insulating film, implanting a first conductivity type impurity of a first concentration into the first polysilicon film, and forming a third insulating film on the first polysilicon film; a first forming of forming, at the same time, an external base lead-out electrode and a gate of a first conductivity type MOS transistor on the semiconductor substrate by etching a stacked film of the first polysilicon film and the third insulating film in predetermined regions; forming a fourth insulating film in the etched, predetermined regions of the stacked film, and, at the same time, forming an external base layer by introducing the first conductivity type impurity of a first concentration into the semiconductor substrate from the external base lead-out electrode of the first conductivity type bipolar transistor; defining, by photolithography, a region where to form an external base lead-out electrode of the first conductivity type bipolar transistor, and forming the link base layer of the first conductivity type bipolar transistor by implanting the first conductivity impurity of a second concentration into the semiconductor substrate in the defined region; a second forming of defining, by photolithography, a first conductivity type MOS transistor forming region where to form the first conductivity type MOS transistor and a second conductivity type bipolar transistor forming region where to form an emitter and a collector of a second conductivity type bipolar transistor, and forming LDD layers in the first conductivity type MOS transistor forming region and an emitter layer and a collector layer in the second conductivity type bipolar transistor forming region by implanting the first conductivity type impurity of a third concentration into the semiconductor substrate in the first conductivity type MOS transistor forming region and the second conductivity type bipolar transistor forming region; forming a fifth insulating film on the films existing after execution of the step of second forming; a frame forming of forming frames on a side face of the external base lead-out electrode of the first conductivity type bipolar transistor and a side face of the gate of the first conductivity type MOS transistor by etching the fifth insulating film; a third forming of defining, by photolithography, a second conductivity type bipolar transistor intrinsic base forming region where to form an intrinsic base of the second conductivity type bipolar transistor and a first conductivity type MOS transistor forming region where to form the first conductivity type MOS transistor, and implanting the first conductivity type impurity of a fourth concentration into the semiconductor substrate in the second conductivity type bipolar transistor intrinsic base forming region and the first conductivity type MOS transistor forming region, to form the emitter layer and the collector layer in the second conductivity type bipolar transistor intrinsic base forming region and to form a source and a drain in the first conductivity type MOS transistor forming region; a sixth insulating film forming of forming a sixth insulating film on predetermined films existing after execution of the step of third forming; defining, by photolithography, a region where to form an external base lead-out electrode of the first conductivity type bipolar transistor, and forming the intrinsic base layer of the first conductivity type bipolar transistor by implanting the first conductivity type impurity of a fifth concentration into the semiconductor substrate in the defined region; a semiconductor substrate exposing of etching the sixth insulating film in the region where to form the external base lead-out electrode of the first conductivity type bipolar transistor, to expose the major surface of the semiconductor substrate there; forming a second polysilicon film on the films existing after execution of the step of semiconductor substrate exposing, implanting a second conductivity type impurity of a first concentration into the second polysilicon film, and forming a seventh insulating film on the second polysilicon film; a fourth forming of forming an emitter lead-out electrode of the first conductivity type bipolar transistor and a gate of a second conductivity type MOS transistor at the same time by etching a stacked film of the seventh insulating film and the second polysilicon film in predetermined regions; a second conductivity type MOS transistor LDD layer forming of defining, by photolithography, a region where to form the second conductivity type MOS transistor, and forming LDD layers of the second conductivity type MOS transistor by implanting the second conductivity type impurity of a second concentration into the semiconductor substrate in the defined region; forming an eighth insulating film on the films existing after execution of the step of second conductivity type MOS transistor LDD layer forming, and forming a frame on a side face of the gate of the second conductivity type MOS transistor by etching the eighth insulating film; a second conductivity type MOS transistor source and drain layers forming of defining, by photolithography, a region where to form the second conductivity type MOS transistor, and forming a source layer and a drain layer of the second conductivity type MOS transistor by implanting the second conductivity type impurity of a third concentration in the semiconductor substrate in the defined region; and forming an interlayer insulating film on the films existing after execution of the step of second conductivity type MOS transistor source and drain layers forming, and forming an emitter layer by diffusing the first conductivity type impurity into the semiconductor substrate from the emitter lead-out electrode of the first conductivity type bipolar transistor.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.